1. Technical Field
Embodiments of the present disclosure may generally relate to a sub word line driver of a semiconductor memory device, and more particularly to a layout of a sub word line driver.
2. Related Art
Generally, a semiconductor memory device consists of a plurality of memory cells and a circuit for controlling the memory cells.
FIG. 1 is a conceptual diagram illustrating an arrangement structure of cell mats MATs for use in a general semiconductor memory device. FIG. 2 is a conceptual diagram illustrating word lines WL arranged in the cell mats MATs.
Referring to FIG. 1, the semiconductor memory device consists of a plurality of mats MATs, each of which has array-shaped memory cells for storing data. Each mat MAT consists of a bit-line sense amplifier BLSA arranged in a row direction to sense/amplify cell data, and a plurality of sub word line drivers SWD arranged in a column direction to enable sub word lines coupled to gates of cell transistors.
Referring to FIG. 2, the respective sub word line drivers SWD may operate word lines WL of the right and left cell mats MAT.